How to assign gpio interrupt? 【Solved】

I’m trying to connect capacitive touchscreen controller FT5206,
which need external gpio interrupt input.

My controller on i2c0, gpio interrupt on PB5.
(No reset control, no wake up control : hardware defined, driver patched)

I’m add to dts :

&i2c0 {
status = “okay”;

    ft5206ge1: touchscreen@38 {
            compatible = "edt,edt-ft5206";
            reg = <0x38>;
            interrupt-parent = <&pio>;
            interrupts = <0 37 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
            touchscreen-size-x = <800>;
            touchscreen-size-y = <480>;
            status = "okay";


When driver (edt-ft5x06.ko) successfully loaded, output of cat /proc/interrupts:

43: 0 sunxi_pio_edge 5 Edge edt-ft5206

Pulses on PB5 are presents , but interrupt counter always 0.

I’m not familiar with dts. What’s wrong?

PB5 is <1 5>, not <0 37> when assigning interrupts with DT.

Changed, but the result is same. Counter always 0.

i’m got access from userspace to port config memory (used mmap).

config data:

PB_CFG0_REG = 0x22677722
: PB5 configured as “PB_EINT5”. Ok.

PB_CFG_EINT0_REG = 0x00000000
PB_CFG_EINT1_REG = 0x00000000
PB_CFG_EINT2_REG = 0x00000000
PB_CFG_EINT3_REG = 0x00000000
: programmed “positive edge” (default), although in dts “IRQ_TYPE_EDGE_FALLING”

PB_EINT_CTL_REG = 0x00000000
: PB5 IRQ enable bit is cleared. It’s normal?

PB_EINT_STATUS_REG = 0x00000020
: PB5 EINT pending bit is set. By my controller. Ok.

So, hardware not properly setup. Problem is in driver (pinctrl), or in dts?

I have idea, try to add (after “interrupts=…”) :
#interrupt-cells = <3>;

That way you will define how many parameters you passing in “interrupts=” parameter.
I don’t know is it critical or not, but in CHIP device tree files they use those, but for IO expander with interrupt controller inside.

Digging deeper in code and looks like there is bug/mistake in PIO IRQ configuration or mistake in documentation.
My research -
By datasheet :
There is 2 PIO Interupts BANKs
Defined - Interupt configuration registers are at offset:
Pn_INT_CFG0 => 0x200+n*0x20+0x00 => PIO Interrrupt Configure Register 0 (header table)
Where ‘n’ is not clear is it PORT or BANK ! (in code if I understand correctly it’s BANK)
So if '‘n’ is BANK then: PB = BANK_0 , PG= BANK_1
PB_INT_CFG0 = 0x200
PG_INT_CFG0 = 0x220
And if ‘n’ is PORT then : PB = 1 , PG = 6
PB_INT_CFG0 = 0x220
PG_INT_CFG0 = 0x2C0

But , later in Datasheet ! :
PB_INT_CFG0 = 0x220
PG_INT_CFG0 = 0x240

So, ‘n’ is BANK + 1 and at this moment I don’t know correct way to change the code.
If anyone is familiar with , your welcome.

If i set PB5 IRQ enable bit : PB_EINT_CTL_REG |= (1<<5)

, and pulse on PB5 is occurs, system freeze.

The problem not only port configuration?

Temporary i’m add (in touchscreen driver) polling instead interrupt.

Found probably most correct solution :
You need to patch kernel :slight_smile:
file : drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
need add line :
.irq_bank_base = 1,

in :
static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
.irq_read_needs_mux = true

So it must look like :
static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
.irq_bank_base = 1,
.irq_read_needs_mux = true

Same as A33 chip have…

This working.

cool name, “resistor” :slight_smile:
in case you are russian, are there any related resource in russian that you know of?
btw did you manage to get your order?

@702 :
Great, I’m happy that it’s working, half day spent on real thing, not useless :slight_smile:
Please mark topic as [Solved] (probably rename topic or somehow)

@exquisitus :
Yes, I am russian but not from Russia. I don’t know any resource in russian about V3s only saw some hw board discussion.
And yes, I got all my orders successfully.

Big work, good result.
I dont’ know, how to mark [Solved]. Need request to administrator.